{"id":809,"date":"2013-09-18T21:55:47","date_gmt":"2013-09-18T21:55:47","guid":{"rendered":"http:\/\/www.antiquetech.com\/?page_id=809"},"modified":"2013-09-18T21:55:47","modified_gmt":"2013-09-18T21:55:47","slug":"intel-chip-markings","status":"publish","type":"page","link":"http:\/\/www.antiquetech.com\/?page_id=809","title":{"rendered":"Intel Chip Markings"},"content":{"rendered":"<h2>Identification Number<\/h2>\n<p>Primary Intel Format:\u00a0 <b>P\u00a0 AB999\u00a0 (V9 or -9)\u00a0\u00a0 \/M<\/b><\/p>\n<table style=\"width: 100%;\" border=\"1\" cellspacing=\"0\" cellpadding=\"2\">\n<tbody>\n<tr>\n<td width=\"20%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>P<\/b><\/span><\/td>\n<td width=\"20%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>A<\/b><\/span><\/td>\n<td width=\"20%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>B<\/b><\/span><\/td>\n<td width=\"10%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>999<\/b><\/span><\/td>\n<td width=\"10%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>(V9 or -9)<\/b><\/span><\/td>\n<td width=\"10%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>\/M<\/b><\/span><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"20%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b>Package *<\/b><\/span><\/td>\n<td valign=\"top\" width=\"20%\"><b>Chip ID #,<\/b><\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\"><b>1st Digit<\/b><\/span><\/td>\n<td valign=\"top\" width=\"20%\"><b>Chip ID #,<\/b><\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\"><b>2nd Digit<\/b><\/span><\/td>\n<td valign=\"top\" width=\"10%\"><b>Chip ID #,<\/b><\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\"><b>Sequence #<\/b><\/span><\/td>\n<td valign=\"top\" width=\"10%\"><b>Version<\/b><\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\"><b>Control<\/b><\/span><\/td>\n<td valign=\"top\" width=\"10%\"><b>Military<\/b><\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\"><b>Spec<\/b><\/span><\/td>\n<\/tr>\n<tr>\n<td valign=\"top\" width=\"20%\"><b>Most Common<\/b><\/p>\n<p>A &#8211; Pin Grid Array<\/p>\n<p>C &#8211; CerDIP<\/p>\n<p>D- Ceramic Sandwich<\/p>\n<p>P &#8211; Polymer Resin<\/p>\n<p>R &#8211; CLCC<\/p>\n<p>N &#8211; PLCC<\/p>\n<p>&nbsp;<\/p>\n<p><b>Others<\/b><\/p>\n<p>Kx &#8211; Plastic Quad Flat Packs<\/p>\n<p>K &amp; Q &#8211; Ceramic\u00a0 Quad Flat Packs<\/p>\n<p>&nbsp;<\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">Others types exist, but are of newer vintages<\/span><\/td>\n<td valign=\"top\" width=\"20%\">0 &#8211; Test Chips \/ NA<\/p>\n<p>1 &#8211; PMOS chip<\/p>\n<p>2 &#8211; NMOS chip<\/p>\n<p>3 &#8211; Bipolar chip<\/p>\n<p>4 &#8211; 4-bit CPU&#8217;s<\/p>\n<p>5 &#8211; CMOS chip<\/p>\n<p>6 &#8211; NA<\/p>\n<p>7 &#8211; Bubble Memory<\/p>\n<p>8 &#8211; 8-bit+ CPU&#8217;s, MCU&#8217;s, Supports<\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">9 &#8211; NA<\/span><\/td>\n<td valign=\"top\" width=\"20%\">0 &#8211; Processors<\/p>\n<p>1 &#8211; RAM<\/p>\n<p>2 &#8211; Support Chip<\/p>\n<p>3 &#8211; ROMs&#8217;<\/p>\n<p>4 &#8211; Shift Registers<\/p>\n<p>5 &#8211; EPLD<\/p>\n<p>6 &#8211; PROM<\/p>\n<p>7 &#8211; EPROM<\/p>\n<p>8 &#8211; Watch\/Timing Chips<\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">9 &#8211; Telecommunications<\/span><\/td>\n<td valign=\"top\" width=\"10%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><span style=\"font-family: Arial,Arial,Helvetica;\">99 or<\/span><\/span>999 or<\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">99-9<\/span><\/td>\n<td valign=\"top\" width=\"10%\">V =<\/p>\n<p>A &#8211; 1st version<\/p>\n<p>B &#8211; 2nd version<\/p>\n<p>etc. or<\/p>\n<p>SX, DX, etc.<\/p>\n<p>&nbsp;<\/p>\n<p>9 =<\/p>\n<p>indicates<\/p>\n<p>sub-version<\/p>\n<p>or<\/p>\n<p>approximate<\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">speed in Mhz<\/span><\/td>\n<td valign=\"top\" width=\"10%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><span style=\"font-family: Arial,Arial,Helvetica;\">A, B, or C<\/span><\/span>&nbsp;<\/p>\n<p>&nbsp;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<p>* Modifiers sometimes found in front of the Package type:<\/p>\n<blockquote><p>A -Automotive temperature range<\/p>\n<p>I &#8211; Industrial Grade<\/p>\n<p>L &#8211; Extended temperature range (-40C to 85C) express product with 160&#215;8 hours burn-in<\/p>\n<p>Q &#8211; Commercial temperature range with (0C to 70C) express product with 160&#215;8 hours burn-in<\/p>\n<p>T &#8211;\u00a0 Extended temperature range (-40C to 85C) express product with no burn-in<\/p><\/blockquote>\n<h2>Date Code<\/h2>\n<p>Intel Date Code Format: <b>YYWW<\/b><\/p>\n<p>These number should be located by themselves with no letters or other numbers immediately adjacent. The numbers are often found on the underside with the country of manufacture.<\/p>\n<p>WW &#8211; Week of manufacture. Ranges from 01 to 52.<\/p>\n<p>YY &#8211; Year of manufacture. Ranges from 73 to 99.<\/p>\n<p>Intel incorporated in 1968. Chips were not produced until 1971. Date codes were not used until 1973.<\/p>\n<h2>Country of Manufacture<\/h2>\n<p>If the chip was not made in the US, it should have the country of manufacture spelled out clearly on the chip.<\/p>\n<table style=\"width: 100%;\" border=\"0\" cellspacing=\"0\" cellpadding=\"0\">\n<tbody>\n<tr>\n<td width=\"75%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><b> Intel had\/has plants in these countries:<\/b><\/span><\/td>\n<td align=\"center\" width=\"25%\"><\/td>\n<\/tr>\n<tr>\n<td rowspan=\"2\" width=\"90%\">&nbsp;<\/p>\n<p><b>Test and Assembly Plants<\/b><\/p>\n<p>Barbados (about 1981-86*)<\/p>\n<p>Costa Rica (Fab A6\/T6), 1998)<\/p>\n<p>Hong Kong (70&#8217;s, subcontractor?)<\/p>\n<p>Penang, Malaysia (1972)<\/p>\n<p>Kulim Hi-Tech Park, Malaysia (1974, &#8220;PC Boards&#8221;)<\/p>\n<p>Shanghai, PR of China (1998)<\/p>\n<p>Manila, Philippines (1983)<\/p>\n<p>Mexico (70&#8217;s, subcontractor?)<\/p>\n<p>USA<\/p>\n<p>&#8211; Chandler, AZ (1996)<\/p>\n<p>&nbsp;<\/p>\n<p><b>Wafer Fab Plants<\/b><\/p>\n<p>Leixlip, Ireland (Fab 10, 1994; Fab 14, 1998, 24, 2000)<\/p>\n<p>Lachish-Kiryat Gat, Israel (Fab 18, 2000)<\/p>\n<p>Jerusalem, Israel (Fab 8, 1985)<\/p>\n<p>USA<\/p>\n<p>&#8211; Chandler, AZ (Fabs 6, 1980-2000, Fab 12, 1997; Fab 22, 2001)<\/p>\n<p>&#8211; Livermore, Ca (Fab 3)<\/p>\n<p>&#8211; Mountain View, Ca (1668-76, &#8220;1st Fab&#8221;)<\/p>\n<p>&#8211; Santa Clara, Ca (Fabs 1, 1971 &amp; 2)<\/p>\n<p>&#8211; Colorado Springs, Co (Fab 23, &#8220;Rockwell&#8221;)<\/p>\n<p>&#8211; Hudson, MA (Fab 17 &#8220;DEC Fab 6&#8221;)<\/p>\n<p>&#8211; Rio Rancho\/Albuquerque, NM (Fabs 7, 1983; 9.1; 9.2; 11)<\/p>\n<p>&#8211; Aloha, Or (Fabs 4, 1976-97 ; 5, 1978; 15)<\/p>\n<p>&#8211; Hilsboro, Or (Fabs 20, 1999)<\/p>\n<p>&#8211; Fort Worth, TX (Fab 16, 2000)<\/td>\n<td align=\"center\" valign=\"bottom\" width=\"10%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" src=\"file:\/\/\/Users\/semery\/Desktop\/Antiquetech\/identification\/intel_date%20code_manuf.jpg\" width=\"250\" height=\"123\" border=\"0\" \/><\/span><\/td>\n<\/tr>\n<tr>\n<td align=\"center\" valign=\"top\" width=\"10%\">\n<p align=\"center\"><span style=\"font-family: Arial,Arial,Helvetica;\">The chip above was assembled in Intel&#8217;s Penang, Malaysia in the 12th week of 1975<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<p>* I have not seen any start\/close dates. These dates are based on observations and best guesses.<\/p>\n<p>&nbsp;<\/p>\n<h2>Copyright Date<\/h2>\n<p>&nbsp;<\/p>\n<p>This is the earliest date that company asserted its copyright to the chip design (there may be multiple dates). Many people confused this date for the date of manufacture. The copyright date and Date Code can differ by 15 years on some chips.<\/p>\n<p>&nbsp;<\/p>\n<table style=\"width: 25%;\" border=\"0\" cellspacing=\"0\" cellpadding=\"0\">\n<tbody>\n<tr>\n<td width=\"100%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" src=\"file:\/\/\/Users\/semery\/Desktop\/Antiquetech\/identification\/intel_copyright.jpg\" width=\"392\" height=\"52\" border=\"0\" \/><\/span><\/td>\n<\/tr>\n<tr>\n<td width=\"100%\"><span style=\"font-family: Arial,Arial,Helvetica;\">Intel Copyrights of 1989 and 1993<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2>Prototype, Pre-production, and Marketing\/Engineering Samples<\/h2>\n<p>Some chips may be released before full production. These chips are usually provided to other companies involved in developing related hardware or software for the new chip. These chips are usually clear marked as &#8220;Prototype&#8221; or &#8220;Pre-production&#8221;.<\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">\u00a0<\/span><\/p>\n<table style=\"width: 100%;\" border=\"0\" cellspacing=\"0\" cellpadding=\"5\">\n<tbody>\n<tr>\n<td rowspan=\"2\" valign=\"top\" width=\"53%\"><span style=\"font-family: Arial,Arial,Helvetica;\">No chip ever made is without design flaws. Chips are released at a given &#8220;Step&#8221; level. If a few of the flaws are fixed the next released version of chip is said to be a higher Step level (often A, B, C, etc. are used). Sometimes chips are marked with a label that indicates the Step level of the chip. Most chips marked with Step levels are pre-production or very early production chips.<\/span><\/td>\n<td align=\"center\" width=\"47%\"><span style=\"font-family: Arial,Arial,Helvetica;\"><img loading=\"lazy\" decoding=\"async\" alt=\"\" src=\"file:\/\/\/Users\/semery\/Desktop\/Antiquetech\/identification\/intel_step.jpg\" width=\"132\" height=\"100\" border=\"0\" \/><\/span><\/td>\n<\/tr>\n<tr>\n<td align=\"center\" width=\"47%\">\n<p align=\"center\">This is a pre-production Intel 8035<\/p>\n<p align=\"center\"><span style=\"font-family: Arial,Arial,Helvetica;\">\u00a0released at Step level C-1A<\/span><\/p>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">Marketing and engineering samples were often provided to large customers. These chip were nominally to be used to evaluate the new chip design. These chips are may have markings that says &#8220;Eng Sample&#8221;, &#8220;Nor for Sale&#8221;, etc. These are often early production chips to used promote the new chip and speed its acceptance.<\/span><\/p>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">\u00a0 <\/span><\/p>\n<h2><span style=\"font-family: Arial,Arial,Helvetica;\">Assembly, Lot, Customer, and Other Control Numbers<\/span><\/h2>\n<p><span style=\"font-family: Arial,Arial,Helvetica;\">Other numbers on the chip are related to internal operations of the company and there for tracking and quality control purposes. Unless you have access to internal company records, these numbers are for the most part useless for collecting and hobbyist purposes.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Identification Number Primary Intel Format:\u00a0 P\u00a0 AB999\u00a0 (V9 or -9)\u00a0\u00a0 \/M P A B 999 (V9 or -9) \/M Package * Chip ID #, 1st Digit Chip ID #, 2nd Digit Chip ID #, Sequence # Version Control Military Spec Most Common A &#8211; Pin Grid Array C &#8211; CerDIP D- Ceramic Sandwich P &#8211; &hellip; <\/p>\n<p><a class=\"more-link block-button\" href=\"http:\/\/www.antiquetech.com\/?page_id=809\">Continue reading &raquo;<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":804,"menu_order":1,"comment_status":"closed","ping_status":"open","template":"","meta":{"footnotes":""},"class_list":["post-809","page","type-page","status-publish","hentry","nodate"],"_links":{"self":[{"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/pages\/809","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=809"}],"version-history":[{"count":1,"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/pages\/809\/revisions"}],"predecessor-version":[{"id":810,"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/pages\/809\/revisions\/810"}],"up":[{"embeddable":true,"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=\/wp\/v2\/pages\/804"}],"wp:attachment":[{"href":"http:\/\/www.antiquetech.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=809"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}